Using Evolutionary Computation to Design the Next Generation of Nano-CMOS Systems

Members: Andy Tyrrell, James Alfred Walker, James Hilder
Website: http://www.nanocmos.ac.uk
Dates: October 2006 - October 2010

Project Description

Progressive scaling of CMOS transistors, as tracked by the International Technology Roadmap for Semiconductors (ITRS) and captured in Moore’s law, has driven the phenomenal success of the semiconductor industry, delivering larger, faster and, cheaper circuits. Silicon technology has now entered the nano-CMOS era with 40 nm MOSFETs already in mass production and sub-10 nm transistors scheduled for production by 2018.

However the years of ‘happy scaling’ are over and the fundamental challenges that the semiconductor industry faces, at both technology and device level, will impinge deeply upon the design of future integrated circuits and systems.

EPSRC in collaboration with leading design houses, chip manufacturers and ECAD vendors is funding a £5.3M project which will apply e-Science and Grid technology to tackle some of the fundamental challenges facing nano-CMOS design. The work at York will study the impact of next generation technologies, and related parameter fluctuations, on the design of digital circuits using evolutionary computation.