Evolvable and Developmental Hardware: Projects
Evolvable hardware offers much for the future of complex system design. Evolutionary techniques not only give the potential to explore larger solution spaces, but when implemented on hardware allow system designs to adapt to changes in the environment, including failures in system components. Our work spans several areas, including the design of evolvable array-based architectures, custom ASIC solutions for intrinsic evolvable hardware, the use of computational development within evolvable hardware, and automatic design of next generation nano-CMOS systems.
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From Biology to Systems Engineering and Electronic DesignMembers: Andy M. Tyrrell, Julian F. Miller, Martin A. Trefzer, Tuze Kuyucu Automatic Design of Adaptive Systems using Unconstrained Evolution and Development on a Hardware Platform: This project aims to use unconstrained evolution and development to automatically design hardware capable of autonomous tasks. The system will be evaluated with complexity and scalability as major considerations. The engineering outcome of this will be adaptable, efficient, fault tolerant systems suitable for future technology. The scientific outcome of this will be data on artificial evolution working in a previously unknown manner, thus helping fundamental research into the origin of biological life and the creation of artificial life. This proposed research has three objectives (i) to design novel mechanisms for "growth" on silicon using unconstrained evolution; (ii) to grow higher-level adaptable entities without human intervention; and (iii) to investigate the properties of such novel ontogenetic/emergent systems and their potential for self-repair and adaptation. |
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PAnDA: Programmable Analogue and Digital ArrayMembers: Andy M. Tyrrell, James Alfred Walker, Martin A. Trefzer PAnDA is a four-year EPSRC funded project that started in October 2010. The project focuses upon one of the greatest challenges in nano-scale electronic design - taking the physical effects of intrinsic variability into account when the shrinking of device sizes approaches atomistic levels in order to achieve functional circuit designs. The proposed research aims to develop understanding of how stochastic variability will affect circuit design in deep sub-micron processes and to propose novel design methodologies to overcome these intrinsic variations. The project will involve the design and fabrication of a novel reconfigurable variability tolerant architecture, which allows variability aware design and rapid prototyping by exploiting the configuration options of the architecture. These are vital steps towards the next generation of FPGA architectures. |
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POEtic: An Evolvable Multi-Purpose Reconfigurable Hardware PlatformMembers: Andy Tyrrell The POEtic project unites Phylogenetic (evolution), Ontogenetic (growth and development) and Epigenetic (learning) abilities within a single reconfigurable hardware device. As part of this project, this work is focused on the efficient combination of evolution and adaptation in a manner which is suitable for implementation in digital hardware. Simple, biologically inspired, Spiking Neural Networks (SNN) have been evolved to provide control signals for a mobile robot. Recent work has involved encoding within each individual's genome the spike timing dependant synaptic plasticity (STDP) update rule for each synaptic connection, where evolution then selects individuals based on their ability to adapt to their environment. Other work has involved looking at audio applications: evolving digital waveguide meshes to provide a simulation of the human vocal tract and synthetic models of plucked strings. |
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Using Evolutionary Computation to Design the Next Generation of Nano-CMOS SystemsMembers: Andy Tyrrell, James Alfred Walker, James Hilder EPSRC in collaboration with leading design houses, chip manufacturers and ECAD vendors is funding a £5.3M project which will apply e-Science and Grid technology to tackle some of the fundamental challenges facing nano-CMOS design. The University partners in this project include the University of Glasgow, the University of Manchester, the University of Southampton, the Intelligent Systems group at the University of York and the University of Edinburgh. The work at York will study the impact of next generation technologies, and related parameter fluctuations, on the design of digital circuits using evolutionary computation. |