The table below shows at what stage of the programme the various modules are taught. Please note timetabling is subject to change.
| Autumn term | Spring term | Summer term | July - September |
|---|---|---|---|
Project Skills: |
Embedded Systems for FPGA |
|
MSc Project |
| Digital Design using VHDL | |||
| Digital Design Techniques | Choose three options from: |
||
| Maths for Signal Processing | Adaptive Signal Processing | ||
| Introduction to Signal Processing | Preparatory Project Work | ||
The majority of these modules are held during the University's terms, however note that the MSc programme is of 12-months duration, and the project and some laboratory courses are undertaken outside term times. The programme will start at the beginning of the Autumn term (usually in early October) and continue until the following September.
For term dates, please see the University term dates page.